README
¶
The cc2500 package provides a Go interface to an SPI-attached
CC2500 module.
The current version supports only the modulation scheme and packet format used by the Dexcom G4 transmitter. Patches to support more general use are welcome.
Note that an antenna must be attached before using the module.
Documentation
¶
Index ¶
- Constants
- Variables
- func CRC8(msg []byte) byte
- func MARCStateName(state byte) string
- func StateName(state byte) string
- type Channel
- type Packet
- type RFConfiguration
- type Radio
- func (r *Radio) Close()
- func (r *Radio) Device() string
- func (r *Radio) DumpRF()
- func (r *Radio) Error() error
- func (r *Radio) Frequency() uint32
- func (r *Radio) Hardware() *radio.Hardware
- func (r *Radio) Init(frequency uint32)
- func (r *Radio) InitRF(frequency uint32)
- func (r *Radio) Name() string
- func (r *Radio) ReadChannelParams() (uint32, uint32)
- func (r *Radio) ReadConfiguration() *RFConfiguration
- func (r *Radio) ReadIF() uint32
- func (r *Radio) ReadMARCState() byte
- func (r *Radio) ReadModemConfig() (bool, uint8, uint32)
- func (r *Radio) ReadNumRXBytes() byte
- func (r *Radio) ReadNumTXBytes() byte
- func (r *Radio) ReadPATable() []byte
- func (r *Radio) ReadRSSI() int
- func (r *Radio) ReadState() byte
- func (r *Radio) Receive(timeout time.Duration) ([]byte, int)
- func (r *Radio) ReceiveReadings() <-chan *Packet
- func (r *Radio) Reset()
- func (r *Radio) Send(data []byte)
- func (r *Radio) SendAndReceive(data []byte, timeout time.Duration) ([]byte, int)
- func (r *Radio) SetError(err error)
- func (r *Radio) SetFrequency(freq uint32)
- func (r *Radio) State() string
- func (r *Radio) Strobe(cmd byte) byte
- func (r *Radio) Version() uint16
- func (r *Radio) WriteConfiguration(config *RFConfiguration)
Constants ¶
View Source
const ( // Crystal frequency in Hz. FXOSC = 26000000 // SPI transaction header bits for read/write and burst/single access. READ_MODE = 1 << 7 BURST_MODE = 1 << 6 // Configuration registers (read/write). IOCFG2 = 0x00 // GDO2 output pin configuration IOCFG1 = 0x01 // GDO1 output pin configuration IOCFG0 = 0x02 // GDO0 output pin configuration FIFOTHR = 0x03 // RX FIFO and TX FIFO thresholds SYNC1 = 0x04 // Sync word, high byte SYNC0 = 0x05 // Sync word, low byte PKTLEN = 0x06 // Packet length PKTCTRL1 = 0x07 // Packet automation control PKTCTRL0 = 0x08 // Packet automation control ADDR = 0x09 // Device address CHANNR = 0x0A // Channel number FSCTRL1 = 0x0B // Frequency synthesizer control FSCTRL0 = 0x0C // Frequency synthesizer control FREQ2 = 0x0D // Frequency control word, high byte FREQ1 = 0x0E // Frequency control word, middle byte FREQ0 = 0x0F // Frequency control word, low byte MDMCFG4 = 0x10 // Modem configuration MDMCFG3 = 0x11 // Modem configuration MDMCFG2 = 0x12 // Modem configuration MDMCFG1 = 0x13 // Modem configuration MDMCFG0 = 0x14 // Modem configuration DEVIATN = 0x15 // Modem deviation setting MCSM2 = 0x16 // Main Radio Control State Machine configuration MCSM1 = 0x17 // Main Radio Control State Machine configuration MCSM0 = 0x18 // Main Radio Control State Machine configuration FOCCFG = 0x19 // Frequency Offset Compensation configuration BSCFG = 0x1A // Bit Synchronization configuration AGCCTRL2 = 0x1B // AGC control AGCCTRL1 = 0x1C // AGC control AGCCTRL0 = 0x1D // AGC control WOREVT1 = 0x1E // High byte Event 0 timeout WOREVT0 = 0x1F // Low byte Event 0 timeout WORCTRL = 0x20 // Wake On Radio control FREND1 = 0x21 // Front end RX configuration FREND0 = 0x22 // Front end TX configuration FSCAL3 = 0x23 // Frequency synthesizer calibration FSCAL2 = 0x24 // Frequency synthesizer calibration FSCAL1 = 0x25 // Frequency synthesizer calibration FSCAL0 = 0x26 // Frequency synthesizer calibration RCCTRL1 = 0x27 // RC oscillator configuration RCCTRL0 = 0x28 // RC oscillator configuration FSTEST = 0x29 // Frequency synthesizer calibration control PTEST = 0x2A // Production test AGCTEST = 0x2B // AGC test TEST2 = 0x2C // Various test settings TEST1 = 0x2D // Various test settings TEST0 = 0x2E // Various test settings )
View Source
const ( // Reset chip. SRES = 0x30 // Enable and calibrate frequency synthesizer // (if MCSM0.FS_AUTOCAL=1). If in RX/TX (with CCA): // Go to a wait state where only the synthesizer is running // (for quick RX / TX turnaround). SFSTXON = 0x31 // Turn off crystal oscillator. SXOFF = 0x32 // Calibrate frequency synthesizer and turn it off. // SCAL can be strobed from IDLE mode without setting // manual calibration mode (MCSM0.FS_AUTOCAL=0) SCAL = 0x33 // Enable RX. Perform calibration first if coming from IDLE // and MCSM0.FS_AUTOCAL=1. SRX = 0x34 // In IDLE state: Enable TX. Perform calibration first if // MCSM0.FS_AUTOCAL=1. If in RX state and CCA is enabled: // Only go to TX if channel is clear. STX = 0x35 // Exit RX / TX, turn off frequency synthesizer and exit // Wake-On-Radio mode if applicable. SIDLE = 0x36 // Perform AFC adjustment of the frequency synthesizer. SAFC = 0x37 // Start automatic RX polling sequence (Wake-on-Radio) // if WORCTRL.RC_PD=0. SWOR = 0x38 // Enter power down mode when CSn goes high. SPWD = 0x39 // Flush the RX FIFO buffer. // Only issue SFRX in IDLE or RXFIFO_OVERFLOW states. SFRX = 0x3A // Flush the TX FIFO buffer. // Only issue SFTX in IDLE or TXFIFO_UNDERFLOW states. SFTX = 0x3B // Reset real time clock to Event1 value. SWORRST = 0x3C // No operation. May be used to get access to the chip status byte. SNOP = 0x3D // Status registers (read-only). // Since these must be read with the burst access bit set, // it is included in the address for simplicity. PARTNUM = 0x70 // Part number for CC2500 VERSION = 0x71 // Current version number FREQEST = 0x72 // Frequency Offset Estimate LQI = 0x73 // Demodulator estimate for Link Quality RSSI = 0x74 // Received signal strength indication MARCSTATE = 0x75 // Control state machine state WORTIME1 = 0x76 // High byte of WOR timer WORTIME0 = 0x77 // Low byte of WOR timer PKTSTATUS = 0x78 // Current GDOx status and packet status VCO_VC_DAC = 0x79 // Current setting from PLL calibration module TXBYTES = 0x7A // Underflow and number of bytes in the TX FIFO RXBYTES = 0x7B // Overflow and number of bytes in the RX FIFO RCCTRL1_STATUS = 0x7C // Last RC oscillator calibration result RCCTRL0_STATUS = 0x7D // Last RC oscillator calibration result // Power amplifier output settings. PATABLE = 0x3E // Transmit and receive FIFOs. TXFIFO = 0x3F RXFIFO = 0x3F // Radio states. STATE_IDLE = 0 STATE_RX = 1 STATE_TX = 2 STATE_FSTXON = 3 STATE_CALIBRATE = 4 STATE_SETTLING = 5 STATE_RXFIFO_OVERFLOW = 6 STATE_TXFIFO_UNDERFLOW = 7 // Status bits 6:4 STATE_MASK = 7 STATE_SHIFT = 4 CHIP_RDY = 1 << 7 GDO2_INV = 1 << 6 GDO2_CFG_MASK = 0x3F GDO1_DS = 1 << 7 GDO1_INV = 1 << 6 GDO1_CFG_MASK = 0x3F GDO0_TEMP_SENSOR_ENABLE = 1 << 7 GDO0_INV = 1 << 6 GDO0_CFG_MASK = 0x3F // FiFOTHR value n corresponds to 4*(n+1) bytes in RX FIFO // or 65 - 4*(n+1) bytes in TX FIFO FIFOTHR_MASK = 0xf PKTCTRL1_PQT_MASK = 7 << 5 PKTCTRL1_PQT_SHIFT = 5 PKTCTRL1_CRC_AUTOFLUSH = 1 << 3 PKTCTRL1_APPEND_STATUS = 1 << 2 PKTCTRL1_ADR_CHK_NONE = 0 << 0 PKTCTRL1_ADR_CHK_NO_BROADCAST = 1 << 0 PKTCTRL1_ADR_CHK_00_BROADCAST = 2 << 0 PKTCTRL1_ADR_CHK_00_FF_BROADCAST = 3 << 0 PKT_APPEND_STATUS_0_RSSI_MASK = 0xFF PKT_APPEND_STATUS_0_RSSI_SHIFT = 0 PKT_APPEND_STATUS_1_CRC_OK = 1 << 7 PKT_APPEND_STATUS_1_LQI_MASK = 0x7F PKT_APPEND_STATUS_1_LQI_SHIFT = 0 PKTCTRL0_WHITE_DATA = 1 << 6 PKTCTRL0_PKT_FORMAT_NORMAL = 0 << 4 PKTCTRL0_PKT_FORMAT_SYNC_SERIAL = 1 << 4 PKTCTRL0_PKT_FORMAT_RANDOM = 2 << 4 PKTCTRL0_PKT_FORMAT_ASYNC_SERIAL = 3 << 4 PKTCTRL0_CRC_EN = 1 << 2 PKTCTRL0_LENGTH_CONFIG_FIXED = 0 << 0 PKTCTRL0_LENGTH_CONFIG_VARIABLE = 1 << 0 PKTCTRL0_LENGTH_CONFIG_INFINITE = 2 << 0 MDMCFG4_CHANBW_E_SHIFT = 6 MDMCFG4_CHANBW_M_SHIFT = 4 MDMCFG4_DRATE_E_SHIFT = 0 MDMCFG3_DRATE_M_SHIFT = 0 MDMCFG2_DEM_DCFILT_OFF = 1 << 7 MDMCFG2_DEM_DCFILT_ON = 0 << 7 MDMCFG2_MOD_FORMAT_MASK = 7 << 4 MDMCFG2_MOD_FORMAT_2_FSK = 0 << 4 MDMCFG2_MOD_FORMAT_GFSK = 1 << 4 MDMCFG2_MOD_FORMAT_ASK_OOK = 3 << 4 MDMCFG2_MOD_FORMAT_MSK = 7 << 4 MDMCFG2_SYNC_MODE_MASK = 7 << 0 MDMCFG2_SYNC_MODE_NONE = 0 << 0 MDMCFG2_SYNC_MODE_15_16 = 1 << 0 MDMCFG2_SYNC_MODE_16_16 = 2 << 0 MDMCFG2_SYNC_MODE_30_32 = 3 << 0 MDMCFG2_SYNC_MODE_NONE_THRES = 4 << 0 MDMCFG2_SYNC_MODE_15_16_THRES = 5 << 0 MDMCFG2_SYNC_MODE_16_16_THRES = 6 << 0 MDMCFG2_SYNC_MODE_30_32_THRES = 7 << 0 MDMCFG1_FEC_EN = 1 << 7 MDMCFG1_FEC_DIS = 0 << 7 MDMCFG1_NUM_PREAMBLE_MASK = 7 << 4 MDMCFG1_NUM_PREAMBLE_2 = 0 << 4 MDMCFG1_NUM_PREAMBLE_3 = 1 << 4 MDMCFG1_NUM_PREAMBLE_4 = 2 << 4 MDMCFG1_NUM_PREAMBLE_6 = 3 << 4 MDMCFG1_NUM_PREAMBLE_8 = 4 << 4 MDMCFG1_NUM_PREAMBLE_12 = 5 << 4 MDMCFG1_NUM_PREAMBLE_16 = 6 << 4 MDMCFG1_NUM_PREAMBLE_24 = 7 << 4 MDMCFG1_CHANSPC_E_MASK = 3 << 0 MDMCFG1_CHANSPC_E_SHIFT = 0 MDMCFG0_CHANSPC_M_SHIFT = 0 DEVIATN_DEVIATION_E_SHIFT = 4 DEVIATN_DEVIATION_M_SHIFT = 0 MCSM2_RX_TIME_RSSI = 1 << 4 MCSM2_RX_TIME_QUAL = 1 << 3 MCSM2_RX_TIME_MASK = 7 << 0 MCSM2_RX_TIME_SHIFT = 0 MCSM2_RX_TIME_END_OF_PACKET = 7 MCSM1_CCA_MODE_ALWAYS = 0 << 4 MCSM1_CCA_MODE_RSSI_BELOW = 1 << 4 MCSM1_CCA_MODE_UNLESS_RECEIVING = 2 << 4 MCSM1_CCA_MODE_RSSI_BELOW_UNLESS_RECEIVING = 3 << 4 MCSM1_RXOFF_MODE_IDLE = 0 << 2 MCSM1_RXOFF_MODE_FSTXON = 1 << 2 MCSM1_RXOFF_MODE_TX = 2 << 2 MCSM1_RXOFF_MODE_RX = 3 << 2 MCSM1_TXOFF_MODE_IDLE = 0 << 0 MCSM1_TXOFF_MODE_FSTXON = 1 << 0 MCSM1_TXOFF_MODE_TX = 2 << 0 MCSM1_TXOFF_MODE_RX = 3 << 0 MCSM0_FS_AUTOCAL_NEVER = 0 << 4 MCSM0_FS_AUTOCAL_FROM_IDLE = 1 << 4 MCSM0_FS_AUTOCAL_TO_IDLE = 2 << 4 MCSM0_FS_AUTOCAL_TO_IDLE_EVERY_4 = 3 << 4 MCSM0_PO_TIMEOUT_SHIFT = 2 MCSM0_PO_TIMEOUT_MASK = 3 << 2 MCSM0_PIN_CTRL_EN = 1 << 1 MCSM0_XOSC_FORCE_ON = 1 << 0 FOCCFG_FOC_BS_CS_GATE = 1 << 5 FOCCFG_FOC_PRE_K_1K = 0 << 3 FOCCFG_FOC_PRE_K_2K = 1 << 3 FOCCFG_FOC_PRE_K_3K = 2 << 3 FOCCFG_FOC_PRE_K_4K = 3 << 3 FOCCFG_FOC_POST_K_PRE_K = 0 << 2 FOCCFG_FOC_POST_K_PRE_K_OVER_2 = 1 << 2 FOCCFG_FOC_LIMIT_0 = 0 << 0 FOCCFG_FOC_LIMIT_BW_OVER_8 = 1 << 0 FOCCFG_FOC_LIMIT_BW_OVER_4 = 2 << 0 FOCCFG_FOC_LIMIT_BW_OVER_2 = 3 << 0 BSCFG_BS_PRE_KI_1KI = 0 << 6 BSCFG_BS_PRE_KI_2KI = 1 << 6 BSCFG_BS_PRE_KI_3KI = 2 << 6 BSCFG_BS_PRE_KI_4KI = 3 << 6 BSCFG_BS_PRE_KP_1KP = 0 << 4 BSCFG_BS_PRE_KP_2KP = 1 << 4 BSCFG_BS_PRE_KP_3KP = 2 << 4 BSCFG_BS_PRE_KP_4KP = 3 << 4 BSCFG_BS_POST_KI_PRE_KI = 0 << 3 BSCFG_BS_POST_KI_PRE_KI_OVER_2 = 1 << 3 BSCFG_BS_POST_KP_PRE_KP = 0 << 2 BSCFG_BS_POST_KP_KP = 1 << 2 BSCFG_BS_LIMIT_0 = 0 << 0 BSCFG_BS_LIMIT_3_125 = 1 << 0 BSCFG_BS_LIMIT_6_25 = 2 << 0 BSCFG_BS_LIMIT_12_5 = 3 << 0 AGCCTRL2_MAX_DVGA_GAIN_ALL = 0 << 6 AGCCTRL2_MAX_DVGA_GAIN_BUT_1 = 1 << 6 AGCCTRL2_MAX_DVGA_GAIN_BUT_2 = 2 << 6 AGCCTRL2_MAX_DVGA_GAIN_BUT_3 = 3 << 6 AGCCTRL2_MAX_LNA_GAIN_0 = 0 << 3 AGCCTRL2_MAX_LNA_GAIN_2_6 = 1 << 3 AGCCTRL2_MAX_LNA_GAIN_6_1 = 2 << 3 AGCCTRL2_MAX_LNA_GAIN_7_4 = 3 << 3 AGCCTRL2_MAX_LNA_GAIN_9_2 = 4 << 3 AGCCTRL2_MAX_LNA_GAIN_11_5 = 5 << 3 AGCCTRL2_MAX_LNA_GAIN_14_6 = 6 << 3 AGCCTRL2_MAX_LNA_GAIN_17_1 = 7 << 3 AGCCTRL2_MAGN_TARGET_24dB = 0 << 0 AGCCTRL2_MAGN_TARGET_27dB = 1 << 0 AGCCTRL2_MAGN_TARGET_30dB = 2 << 0 AGCCTRL2_MAGN_TARGET_33dB = 3 << 0 AGCCTRL2_MAGN_TARGET_36dB = 4 << 0 AGCCTRL2_MAGN_TARGET_38dB = 5 << 0 AGCCTRL2_MAGN_TARGET_40dB = 6 << 0 AGCCTRL2_MAGN_TARGET_42dB = 7 << 0 AGCCTRL1_AGC_LNA_PRIORITY_0 = 0 << 6 AGCCTRL1_AGC_LNA_PRIORITY_1 = 1 << 6 AGCCTRL1_CARRIER_SENSE_REL_THR_DISABLE = 0 << 4 AGCCTRL1_CARRIER_SENSE_REL_THR_6DB = 1 << 4 AGCCTRL1_CARRIER_SENSE_REL_THR_10DB = 2 << 4 AGCCTRL1_CARRIER_SENSE_REL_THR_14DB = 3 << 4 AGCCTRL1_CARRIER_SENSE_ABS_THR_0DB = 0x0 << 0 AGCCTRL1_CARRIER_SENSE_ABS_THR_1DB_ABOVE = 0x1 << 0 AGCCTRL1_CARRIER_SENSE_ABS_THR_2DB_ABOVE = 0x2 << 0 AGCCTRL1_CARRIER_SENSE_ABS_THR_3DB_ABOVE = 0x3 << 0 AGCCTRL1_CARRIER_SENSE_ABS_THR_4DB_ABOVE = 0x4 << 0 AGCCTRL1_CARRIER_SENSE_ABS_THR_5DB_ABOVE = 0x5 << 0 AGCCTRL1_CARRIER_SENSE_ABS_THR_6DB_ABOVE = 0x6 << 0 AGCCTRL1_CARRIER_SENSE_ABS_THR_7DB_ABOVE = 0x7 << 0 AGCCTRL1_CARRIER_SENSE_ABS_THR_DISABLE = 0x8 << 0 AGCCTRL1_CARRIER_SENSE_ABS_THR_7DB_BELOW = 0x9 << 0 AGCCTRL1_CARRIER_SENSE_ABS_THR_6DB_BELOW = 0xA << 0 AGCCTRL1_CARRIER_SENSE_ABS_THR_5DB_BELOW = 0xB << 0 AGCCTRL1_CARRIER_SENSE_ABS_THR_4DB_BELOW = 0xC << 0 AGCCTRL1_CARRIER_SENSE_ABS_THR_3DB_BELOW = 0xD << 0 AGCCTRL1_CARRIER_SENSE_ABS_THR_2DB_BELOW = 0xE << 0 AGCCTRL1_CARRIER_SENSE_ABS_THR_1DB_BELOW = 0xF << 0 AGCCTRL0_HYST_LEVEL_NONE = 0 << 6 AGCCTRL0_HYST_LEVEL_LOW = 1 << 6 AGCCTRL0_HYST_LEVEL_MEDIUM = 2 << 6 AGCCTRL0_HYST_LEVEL_HIGH = 3 << 6 AGCCTRL0_WAIT_TIME_8 = 0 << 4 AGCCTRL0_WAIT_TIME_16 = 1 << 4 AGCCTRL0_WAIT_TIME_24 = 2 << 4 AGCCTRL0_WAIT_TIME_32 = 3 << 4 AGCCTRL0_AGC_FREEZE_NORMAL = 0 << 2 AGCCTRL0_AGC_FREEZE_SYNC = 1 << 2 AGCCTRL0_AGC_FREEZE_MANUAL_ANALOG = 2 << 2 AGCCTRL0_AGC_FREEZE_MANUAL_BOTH = 3 << 2 AGCCTRL0_FILTER_LENGTH_8 = 0 << 0 AGCCTRL0_FILTER_LENGTH_16 = 1 << 0 AGCCTRL0_FILTER_LENGTH_32 = 2 << 0 AGCCTRL0_FILTER_LENGTH_64 = 3 << 0 FREND1_LNA_CURRENT_SHIFT = 6 FREND1_LNA2MIX_CURRENT_SHIFT = 4 FREND1_LODIV_BUF_CURRENT_RX_SHIFT = 2 FREND1_MIX_CURRENT_SHIFT = 0 FREND0_LODIV_BUF_CURRENT_TX_MASK = 3 << 4 FREND0_LODIV_BUF_CURRENT_TX_SHIFT = 4 FREND0_PA_POWER_MASK = 7 FREND0_PA_POWER_SHIFT = 0 TEST2_NORMAL_MAGIC = 0x88 TEST2_RX_LOW_DATA_RATE_MAGIC = 0x81 TEST1_TX_MAGIC = 0x31 TEST1_RX_LOW_DATA_RATE_MAGIC = 0x35 TEST0_7_2_MASK = 0xFC TEST0_VCO_SEL_CAL_EN = 1 << 1 TEST0_0_MASK = 1 LQI_CRC_OK = 1 << 7 LQI_LQI_EST_MASK = 0x7F MARCSTATE_MASK = 0x1F MARCSTATE_SLEEP = 0x00 MARCSTATE_IDLE = 0x01 MARCSTATE_VCOON_MC = 0x03 MARCSTATE_REGON_MC = 0x04 MARCSTATE_MANCAL = 0x05 MARCSTATE_VCOON = 0x06 MARCSTATE_REGON = 0x07 MARCSTATE_STARTCAL = 0x08 MARCSTATE_BWBOOST = 0x09 MARCSTATE_FS_LOCK = 0x0A MARCSTATE_IFADCON = 0x0B MARCSTATE_ENDCAL = 0x0C MARCSTATE_RX = 0x0D MARCSTATE_RX_END = 0x0E MARCSTATE_RX_RST = 0x0F MARCSTATE_TXRX_SWITCH = 0x10 MARCSTATE_RX_OVERFLOW = 0x11 MARCSTATE_FSTXON = 0x12 MARCSTATE_TX = 0x13 MARCSTATE_TX_END = 0x14 MARCSTATE_RXTX_SWITCH = 0x15 MARCSTATE_TX_UNDERFLOW = 0x16 PKTSTATUS_CRC_OK = 1 << 7 PKTSTATUS_CS = 1 << 6 PKTSTATUS_PQT_REACHED = 1 << 5 PKTSTATUS_CCA = 1 << 4 PKTSTATUS_SFD = 1 << 3 PKTSTATUS_GDO2 = 1 << 2 PKTSTATUS_GDO0 = 1 << 0 ENCCCS_MODE_CBC = 0 << 4 ENCCCS_MODE_CFB = 1 << 4 ENCCCS_MODE_OFB = 2 << 4 ENCCCS_MODE_CTR = 3 << 4 ENCCCS_MODE_ECB = 4 << 4 ENCCCS_MODE_CBC_MAC = 5 << 4 ENCCCS_RDY = 1 << 3 ENCCCS_CMD_ENCRYPT = 0 << 1 ENCCCS_CMD_DECRYPT = 1 << 1 ENCCCS_CMD_LOAD_KEY = 2 << 1 ENCCCS_CMD_LOAD_IV = 3 << 1 ENCCCS_START = 1 << 0 NUM_TXBYTES_MASK = 0x7F TXFIFO_UNDERFLOW = 1 << 7 NUM_RXBYTES_MASK = 0x7F RXFIFO_OVERFLOW = 1 << 7 )
Variables ¶
View Source
var ( // ErrRXFIFOOverflow indicates a RXFIFO overflow condition. ErrRXFIFOOverflow = errors.New("RXFIFO overflow") // ErrTXFIFOUnderflow indicates a TXFIFO underflow condition. ErrTXFIFOUnderflow = errors.New("TXFIFO underflow") )
View Source
var ( // Channels contains the channel numbers for the listed frequencies, // assuming 250 kHz channel spacing. // The initial FSCTRL0 offsets were determined empirically. Channels = []Channel{ {000, 0xFD}, {100, 0xFD}, {199, 0xFD}, {209, 0xFD}, } )
View Source
var ErrReceiveTimeout = errors.New("receive timeout")
ErrReceiveTimeout indicates that a Receive operation timed out.
View Source
var ResetRFConfiguration = RFConfiguration{ IOCFG2: 0x29, IOCFG1: 0x2E, IOCFG0: 0x3F, FIFOTHR: 0x07, SYNC1: 0xD3, SYNC0: 0x91, PKTLEN: 0xFF, PKTCTRL1: 1 << 2, PKTCTRL0: 1<<6 | 1<<2 | 1<<0, ADDR: 0x00, CHANNR: 0x00, FSCTRL1: 0x0F, FSCTRL0: 0x00, FREQ2: 0x5E, FREQ1: 0xC4, FREQ0: 0xEC, MDMCFG4: 2<<6 | 0xC<<0, MDMCFG3: 0x22, MDMCFG2: 0x02, MDMCFG1: 2<<4 | 2<<0, MDMCFG0: 0xF8, DEVIATN: 4<<4 | 7<<0, MCSM2: 0x07, MCSM1: 3 << 4, MCSM0: 1 << 2, FOCCFG: 1<<6 | 1<<5 | 2<<3 | 1<<2 | 2<<0, BSCFG: 1<<6 | 2<<4 | 1<<3 | 1<<2, AGCCTRL2: 0x03, AGCCTRL1: 1 << 6, AGCCTRL0: 2<<6 | 1<<4 | 1<<0, WOREVT1: 0x87, WOREVT0: 0x6B, WORCTRL: 1<<7 | 7<<4 | 1<<3, FREND1: 1<<6 | 1<<4 | 1<<2 | 2<<0, FREND0: 1 << 4, FSCAL3: 2<<6 | 2<<4 | 9<<0, FSCAL2: 0x0A, FSCAL1: 0x20, FSCAL0: 0x0D, RCCTRL1: 0x41, RCCTRL0: 0x00, FSTEST: 0x59, PTEST: 0x7F, AGCTEST: 0x3F, TEST2: 0x88, TEST1: 0x31, TEST0: 2<<2 | 1<<1 | 1<<0, }
ResetRFConfiguration contains the register values after reset, according to data sheet section 32.1.
Functions ¶
func MARCStateName ¶
MARCStateName converts a MARC state value to a string.
Types ¶
type Channel ¶
type Channel struct {
// contains filtered or unexported fields
}
Channel contains information about a channel register and frequency offset.
type Packet ¶
type Packet struct {
Timestamp time.Time
Channel int
Data []byte
TransmitterID string
Raw uint32
Filtered uint32
Battery uint8
RSSI int
}
Packet represents a Dexcom G4 packet.
type RFConfiguration ¶
type RFConfiguration struct {
IOCFG2 byte // GDO2 output pin configuration
IOCFG1 byte // GDO1 output pin configuration
IOCFG0 byte // GDO0 output pin configuration
FIFOTHR byte // RX FIFO and TX FIFO thresholds
SYNC1 byte // Sync word, high byte
SYNC0 byte // Sync word, low byte
PKTLEN byte // Packet length
PKTCTRL1 byte // Packet automation control
PKTCTRL0 byte // Packet automation control
ADDR byte // Device address
CHANNR byte // Channel number
FSCTRL1 byte // Frequency synthesizer control
FSCTRL0 byte // Frequency synthesizer control
FREQ2 byte // Frequency control word, high byte
FREQ1 byte // Frequency control word, middle byte
FREQ0 byte // Frequency control word, low byte
MDMCFG4 byte // Modem configuration
MDMCFG3 byte // Modem configuration
MDMCFG2 byte // Modem configuration
MDMCFG1 byte // Modem configuration
MDMCFG0 byte // Modem configuration
DEVIATN byte // Modem deviation setting
MCSM2 byte // Main Radio Control State Machine configuration
MCSM1 byte // Main Radio Control State Machine configuration
MCSM0 byte // Main Radio Control State Machine configuration
FOCCFG byte // Frequency Offset Compensation configuration
BSCFG byte // Bit Synchronization configuration
AGCCTRL2 byte // AGC control
AGCCTRL1 byte // AGC control
AGCCTRL0 byte // AGC control
WOREVT1 byte // High byte Event 0 timeout
WOREVT0 byte // Low byte Event 0 timeout
WORCTRL byte // Wake On Radio control
FREND1 byte // Front end RX configuration
FREND0 byte // Front end TX configuration
FSCAL3 byte // Frequency synthesizer calibration
FSCAL2 byte // Frequency synthesizer calibration
FSCAL1 byte // Frequency synthesizer calibration
FSCAL0 byte // Frequency synthesizer calibration
RCCTRL1 byte // RC oscillator configuration
RCCTRL0 byte // RC oscillator configuration
FSTEST byte // Frequency synthesizer calibration control
PTEST byte // Production test
AGCTEST byte // AGC test
TEST2 byte // Various test settings
TEST1 byte // Various test settings
TEST0 byte // Various test settings
}
RFConfiguration represents the radio's configuration registers.
func (*RFConfiguration) Bytes ¶
func (config *RFConfiguration) Bytes() []byte
Bytes returns the RFConfiguration as a byte slice.
type Radio ¶
type Radio struct {
// contains filtered or unexported fields
}
Radio represents an open radio device.
func (*Radio) InitRF ¶
InitRF initializes the radio to communicate with a Dexcom G4 continuous glucose monitor at the given frequency.
func (*Radio) ReadChannelParams ¶
ReadChannelParams returns the radio's channel bandwidth and data rate.
func (*Radio) ReadConfiguration ¶
func (r *Radio) ReadConfiguration() *RFConfiguration
ReadConfiguration reads the current RFConfiguration from the radio.
func (*Radio) ReadMARCState ¶
ReadMARCState returns the radio's MARC state.
func (*Radio) ReadModemConfig ¶
ReadModemConfig returns the radio's modem configuration: whether FEC is enabled, the minimum preamble length, and the channel spacing.
func (*Radio) ReadNumRXBytes ¶
ReadNumRXBytes reads the RXBYTES register and detects RXFIFO overflow.
func (*Radio) ReadNumTXBytes ¶
ReadNumTXBytes reads the TXBYTES register and detects TXFIFO underflow.
func (*Radio) ReadPATable ¶
ReadPATable returns the contents of PATABLE.
func (*Radio) Receive ¶
Receive listens with the given timeout for an incoming packet. It returns the packet and the associated RSSI. Packet layout in RX FIFO:
0: length byte (n) 1..n: packet body n+1: RSSI n+2: CRC OK and LQI
2-byte CRC following packet body is checked and stripped in hardware.
func (*Radio) ReceiveReadings ¶
ReceiveReadings starts a goroutine to listen for incoming packets and returns a channel that can be used to receive them.
func (*Radio) SendAndReceive ¶
SendAndReceive transmits the given packet, then listens with the given timeout for an incoming packet. It returns the packet and the associated RSSI.
func (*Radio) SetFrequency ¶
SetFrequency sets the radio to the given frequency, in Hertz.
func (*Radio) WriteConfiguration ¶
func (r *Radio) WriteConfiguration(config *RFConfiguration)
WriteConfiguration writes the given RFConfiguration to the radio.
Source Files
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